The present invention relates generally to integrated circuit ("IC") devices, or chips, and more specifically to a system for distributing synchronous clock signals on a chip using asynchronous FIFO memory circuits.
ICs are built from single chips of semiconductor material. A single IC chip contains a number of electrical components, such as diodes, transistors and resistors, built into the semiconductor material. Today, Very Large-Scale Integrated (VLSI) circuit chips contain hundreds of thousands of transistors and other components arranged in arrays and built directly onto the chip.
Interconnected chip components usually operate under a synchronization system in order to function properly. For example, a simple serial bank of flip-flop memory registers successively accesses and transfers data elements according to a predetermined clock cycle. Every cycle of the clock signal, each register turns on and performs a function, such as accessing information from a data source, storing the data, or transferring the data to the next register. Flip-flop memory circuits are just one example of interconnected components that operate under a synchronized environment according to a common clock signal.
Synchronized components on a chip are traditionally clocked from a single clock source. A clock device, normally a separate oscillator chip or circuit, distributes a clock signal to components on the chip from a single clock source, and the signal from that clock source is distributed to various locations around the chip by a system of signal lines. Buffers or repeaters may be added depending on the number of locations to be clocked or their relative distances from the clock source.
A major problem affecting the synchronization of multiple components is clock skew. Skew is a relative timing deviation, either in phase or in frequency, between a given clock signal and a reference signal. The reference signal is often the clock source. One cause of clock skew is the varying distances between components to be clocked and the clock source. Signal delay, a function of electrical path length, causes the clock signal to arrive at components near the clock source earlier than at more distant components. Clock skew can be avoided by placing all clocked components the same distance from the clock source, but such placement is rarely possible given the constraints of chip layout and circuit design. Clock signal buffers and repeaters, which require their own power source and control circuitry, also add delay to the distributed clock signal. Further, because buffers and repeaters have inherent performance variances, it is infeasible to employ them in an a scheme to equalize clock signal timing.
The trend is toward building larger VLSI semiconductor chips with many times more components, all of which are being operated under increasingly faster computing speeds. At faster computing speeds, clock signal frequency increases, resulting in less time between successive clock cycles. With less time between clock cycles, any clock skew would represent a greater portion of a clock cycle. Therefore, what is needed is a more precise clock system which can minimize skew to avoid disruptions in synchronized chip operations.